The present invention relates to an input circuit, and particularly to an input circuit that is low in loss, easy to take AC coupling and provides less power consumption.
As an example of a conventional input circuit, three has been known one disclosed in the following literature.
“Low Power-Consumption 10 Gb/s EA Modulator Driver IC”, 1998 Society Conference of the Institute of Electronics, Information and Communication Engineers, C-10-16, p63
An input circuit section of a circuit shown in FIG. 1 of the present literature has been described as a conventional circuit in FIG. 5. The conventional input circuit will be explained below while referring to FIG. 5.
A signal input terminal IN is connected to one electrode of an input terminating resistor R1 and the gate of a first field effect transistor (hereinafter called an “FET”) Q1. The other electrode of the input terminating resistor R1 and the drain of the first FET Q1 are connected to a ground GND. The source of the first FET Q1 is connected to the anode of a level shift diode D1. The cathode of the level shift diode D1 is connected to an output terminal OUT and the drain of a second FET Q2. The gate and source of the second FET Q2 are connected to a negative potential source VS.
In the circuit shown in FIG. 5, the first FET Q1 operates as a drain grounded amplifier, and the second FET Q2 is a source follower circuit operated as a current source. A signal inputted to the input terminal IN is reduced in potential by the level shift diode D1, which in turn is outputted to the output terminal OUT. The input circuit shown in FIG. 5 is connected to a pre-stage circuit in the form of CML (Current Mode Logic) coupling. In this case, the input circuit operates according to the flowing of a current signal lin of the pre-stage circuit into the terminating circuit R1.
Assuming that a gate-to-source voltage of an FET is given as vgs, a drain-to-source voltage thereof is given as vds, a mutual conductance thereof is given as gm and a drain conductance thereof is given as gd, a drain current id of the FET is generally represented by the following [equation 1].id=gm*(vgs−vth)+gd*vds  [equation 1]
Let's assume that in FIG. 5, an input voltage is represented as vin, an output voltage is represented as vout, a level shift voltage of the level shift diode D1 is represented as vf, mutual conductances of the first and second FETs Q1 and Q2 are represented as gm, drain conductances thereof are represented as gd, threshold voltages of the first and second FETs Q1 and Q2 are represented as vth, and a voltage value of the negative potential source VS is represented as vs, respectively, and each of the first and second FETs Q1 and Q2 is operated in a saturated region. A drain current id1 of the first FET Q1 is represented by the following [equation 2]:id1=gm*(vin−vout+vf−vth)+gd*(vf−vout)  [equation 2]
Further, a drain current id2 of the second FET Q2 is represented by the following [equation 3]:id2=gm*(−vth)+gd*(vout−vs)  [equation 3]
Since id1=id2 in the case of the source follower circuit herein, the output voltage is given by the [equation 2] and [equation 3] as follows:vout={gm/(gm+2*gd)}*vin+{gd*vs+(gm+gd)*vf}/(gm+2·gd)  [equation 4]A loss LS1 of this circuit is determined by differentiating the [equation 4] with vin, which is represented as follows:LS1=gm/(gm+2*gd)  [equation 5]
However, the above-described input circuit is high in loss as represented by the [equation 5]. Assuming that as numerical examples, for example, the mutual conductance gm of the FET is 500 mS (Siemens: reciprocal of Ω) per gate width of 1 mm, and the drain conductance gd of the FET is 30 mS per gate width of 1 mm, the loss results in 0.98 dB from the [equation 5].
Since the gate voltage of the first FET Q1 takes the same potential as the ground where the above-described input circuit and pre-stage circuit are connected to each other in the form of AC coupling, an operating point of the first FET Q1 results in an FET's linear region, thus causing a problem that the loss further increases.
Further, when the current of the current source is reduced in the case of the conventional input circuit, the operating point of the first FET Q1 changes and the mutual conductance gm is lowered. Thus, a problem arises in that since the first FET Q1 is degraded in drive capacity, the current cannot be cut down.